Motorola MTM5000 series firmwares lack properly configured memory protection of pages shared between the OMAP-L138 ARM and DSP cores. The SoC provides two memory protection units, MPU1 and MPU2, to enforce the trust boundary between the two cores. Since both units are left unconfigured by the firmwares, an adversary with control over either core can trivially gain code execution on the other, by overwriting code located in shared RAM or DDR2 memory regions.
CVE-2022-27813
Score 8.1 from GitHub Security Advisory (severity: HIGH) published 2023-10-19. NVD baseline CVSS 8.1; sources differ by 0.0.
- High severity, but no confirmed exploitation yet
No vendor fix yet — apply a workaround or compensating control (WAF / firewall / segmentation) and watch for a patch.
- CVSS v3
- 8.1
- EG Score
- 8.1(medium)
- EPSS
- 7.6%
- KEV
- Not listed
Published
October 19, 2023
Last Modified
November 21, 2024
References (2)
- cert@ncschttps://tetraburst.com/
- af854a3a-2127-422b-91ae-364da2661108https://tetraburst.com/
Weakness Classification(1)
MITRE Common Weakness Enumeration — the root-cause categories this CVE belongs to.
Data Freshness Timeline
(refreshed 11× in last 7d / 45× in last 30d)
Each row is a source pipeline that fetched or updated this CVE on that date, with what changed. For example, "NVD update" means NVD published or revised its analysis for this CVE; "MITRE cvelistV5" means we ingested or refreshed it from the CNA feed. Most recent first.
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- 2026-05-24 15:30 UTCEG score recompute
- 2026-05-24 15:30 UTCGHSA enrichment
Frequently asked(5)
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